Hey! I’m using LX2162A Clearfog which seems to support DDR ECC functionality.
But after booting prebuild SolidRun’s image I see in log messages that ECC is turned off.
The LX2162a SOM supports ECC but by default our SOMs are not produced in this configuration. ECC memory support can be ordered as an option at quantity.
My LX2162A SOM has 9 DDR chip installed on it. I guess that 8 chips for 8GB DDR and one for ECC support? Or besides the 9th DDR chip for ECC there is another HW configuration that is required for ECC support?
@jnettlet - Looks like SPD EEPROM installed on LX2162A SOM contains configuration with disabled ECC despite that SOM supports ECC (there is 9th DDR chip installed). Is it possible to get binary for SPD EEPROM with enabled ECC support?
I have forwarded the question to the hardware team regarding the current ECC testing status of the SOM. It is possible that the hardware was enabled in early production but the full ECC testing has not been verified.
So ECC support is available but it is currently disabled by default. We are discussing internally how we want to enable it. We should have something ready next week.
Weird, its said in these boards description that they do support ecc ram,
i mean it’s controller is supposed to be into the soc and not the pcb?.
So why turn it off?.
If it can be left optional
There is no runtime mechanism to turn on and off ECC memory, although theoretically this could be possible. ECC was disabled in the default builds for performance reasons.
Well its probably gonna be a top thing for those using it as a nas system or web server.
Or maybe a data crunching machine (damn the possibilities are endless).
That is why support for ECC was included in the hardware. However I don’t have access to that hardware platform so the hardware enablement team working on the project will need to make the necessary changes to the BSP
Hello!
I was able to enable the ECC support on the LX2162A SOM (9 DDR4 chips variant) by modifying the DDR SPD data, replacing byte 13 “Module Memory Bus Width” of it with the 0x0B value (instead of the 0x03 value that was there previously). After this modification, it looks like the ECC feature appears enabled in all boot stages; both ATF BL2, U-Boot, and the Linux EDAC module report that the ECC feature is enabled.
But still, to be completely sure that it will work correctly, I’d like to know: is SPD data modification sufficient for proper activation of the ECC feature? Is any additional software or hardware modification required for the DDR ECC feature to work properly? Is the difference between the SOMs produced with ECC support and without it only in the SPD data contents?
Yes that is all that should be required. This is all driven by the memory initialization and calibration routines in TF-A which are configured through the SPD data.
