Poking around a bunch but haven’t found a clear answer to this one so figured I would ask the ether.
The default initialization images have a SERDES configuration of 8_5_2. SD3 protocol 2 means than PCIe controller 5 and 6 are x4 lanes but the Honeycomb carrier board has an x8 link, the block diagram shows all 8 lanes of SD3 connected. Should the init image for this board utilize SD3 protocol 1?
As you can see in the NXP LX2160A reference manual SERDES configuration 2 on SD3 is for the x8 PCIe lanes. SERDES configuration 3 is for the 2 x x4 ports, and you can see it is used for our lx2160a_uefi images that are built to support PCIe bifurcation.
Thank you for the quick answer!
Is the information provided here incorrect then?
It says SD3 protocol 0 is OFF, 1 is x8, and 2 is x4/x4
Yes, I will have it updated. In general if there are any questions please cross reference the NXP reference manual. It is freely available with registration.
Thank you again so much!
