How to set EP mode on PCIe in Honeycomb LX2?

rbasso · September 2, 2024, 2:16pm

Hello,

I have been attempting to configure the PCIe controller as an EP, but so far, I haven’t had success. Despite making the modifications listed below, I am still unable to see the controller under /sys/kernel/config/pci_ep/controllers.

Could you please let me know if there’s anything I might be missing? I would greatly appreciate any insights you could provide.

Changes to within _build/linux :

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 048500ecec8d..6c944be3ce0e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1197,7 +1197,7 @@
 			reg-names = "regs", "addr_space";
 			apio-wins = <256>;
 			max-functions = /bits/ 8 <2>;
-			status = "disabled";
+			status = "okay";
 		};
 
 		pcie4: pcie@3700000 {
@@ -1276,7 +1276,7 @@
 			reg-names = "regs", "addr_space";
 			apio-wins = <256>;
 			max-functions = /bits/ 8 <2>;
-			status = "disabled";
+			status = "okay";
 		};
 
 		pcie6: pcie@3900000 {

Changes to _build/u-boot :

diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 1b1ef683b70..05e21b311b1 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -364,95 +364,24 @@
 
 	};
 
-	pcie1: pcie@3400000 {
-		compatible = "fsl,lx2160a-pcie";
-		reg = <0x00 0x03400000 0x0 0x80000   /* PAB registers */
-		       0x00 0x03480000 0x0 0x40000   /* LUT registers */
-		       0x00 0x034c0000 0x0 0x40000   /* PF control registers */
-		       0x80 0x00000000 0x0 0x2000>; /* configuration space */
-		reg-names = "ccsr", "lut", "pf_ctrl", "config";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		bus-range = <0x0 0xff>;
-		ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000   /* downstream I/O */
-			  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-	};
-
-	pcie2: pcie@3500000 {
-		compatible = "fsl,lx2160a-pcie";
-		reg = <0x00 0x03500000 0x0 0x80000   /* PAB registers */
-		       0x00 0x03580000 0x0 0x40000   /* LUT registers */
-		       0x00 0x035c0000 0x0 0x40000   /* PF control registers */
-		       0x88 0x00000000 0x0 0x2000>; /* configuration space */
-		reg-names = "ccsr", "lut", "pf_ctrl", "config";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		num-lanes = <2>;
-		bus-range = <0x0 0xff>;
-		ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000   /* downstream I/O */
-			  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-	};
-
-	pcie3: pcie@3600000 {
-		compatible = "fsl,lx2160a-pcie";
-		reg = <0x00 0x03600000 0x0 0x80000   /* PAB registers */
-		       0x00 0x03680000 0x0 0x40000   /* LUT registers */
-		       0x00 0x036c0000 0x0 0x40000   /* PF control registers */
-		       0x90 0x00000000 0x0 0x2000>; /* configuration space */
-		reg-names = "ccsr", "lut", "pf_ctrl", "config";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		bus-range = <0x0 0xff>;
-		ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000   /* downstream I/O */
-			  0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-	};
-
-	pcie4: pcie@3700000 {
-		compatible = "fsl,lx2160a-pcie";
-		reg = <0x00 0x03700000 0x0 0x80000   /* PAB registers */
-		       0x00 0x03780000 0x0 0x40000   /* LUT registers */
-		       0x00 0x037c0000 0x0 0x40000   /* PF control registers */
-		       0x98 0x00000000 0x0 0x2000>; /* configuration space */
-		reg-names = "ccsr", "lut", "pf_ctrl", "config";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		bus-range = <0x0 0xff>;
-		ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000   /* downstream I/O */
-			  0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-	};
-
-	pcie5: pcie@3800000 {
-		compatible = "fsl,lx2160a-pcie";
-		reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
-		       0x00 0x03880000 0x0 0x40000   /* LUT registers */
-		       0x00 0x038c0000 0x0 0x40000   /* PF control registers */
-		       0xa0 0x00000000 0x0 0x2000>; /* configuration space */
-		reg-names = "ccsr", "lut", "pf_ctrl", "config";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		bus-range = <0x0 0xff>;
-		ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000   /* downstream I/O */
-			  0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-	};
-
-	pcie6: pcie@3900000 {
-		compatible = "fsl,lx2160a-pcie";
-		reg = <0x00 0x03900000 0x0 0x80000   /* PAB registers */
-		       0x00 0x03980000 0x0 0x40000   /* LUT registers */
-		       0x00 0x039c0000 0x0 0x40000   /* PF control registers */
-		       0xa8 0x00000000 0x0 0x2000>; /* configuration space */
-		reg-names = "ccsr", "lut", "pf_ctrl", "config";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		bus-range = <0x0 0xff>;
-		ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000   /* downstream I/O */
-			  0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	pcie_ep3: pcie_ep@3600000 {
+		compatible = "fsl,lx2160a-pcie-ep";
+		reg = <0x00 0x03600000 0x0 0x00100000
+		       0x90 0x00000000 0x8 0x00000000>;
+		reg-names = "regs", "addr_space";
+		apio-wins = <256>;
+		max-functions = /bits/ 8 <2>;
+		status = "okay";
+	};
+
+	pcie_ep5: pcie_ep@3800000 {
+		compatible = "fsl,lx2160a-pcie-ep";
+		reg = <0x00 0x03800000 0x0 0x00100000
+		       0xa0 0x00000000 0x8 0x00000000>;
+		reg-names = "regs", "addr_space";
+		apio-wins = <256>;
+		max-functions = /bits/ 8 <2>;
+		status = "okay";
 	};
 
 	fsl_mc: fsl-mc@80c000000 {
diff --git a/arch/arm/dts/fsl-lx2162a-clearfog.dts b/arch/arm/dts/fsl-lx2162a-clearfog.dts
index 2b6ea0a2067..b71a5bd2f9a 100644
--- a/arch/arm/dts/fsl-lx2162a-clearfog.dts
+++ b/arch/arm/dts/fsl-lx2162a-clearfog.dts
@@ -348,16 +348,6 @@
 	};
 };
 
-/* CON7 */
-&pcie4 {
-	status = "disabled";
-};
-
-/* CON8 */
-&pcie3 {
-	status = "disabled";
-};
-
 &sata0 {
 	status = "disabled";
 };
diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts
index 0ca30df8620..410a50b655f 100644
--- a/arch/arm/dts/fsl-lx2162a-qds.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
@@ -25,18 +25,6 @@
 	status = "disabled";
 };
 
-&pcie2 {
-	status = "disabled";
-};
-
-&pcie5 {
-	status = "disabled";
-};
-
-&pcie6 {
-	status = "disabled";
-};
-
 &dspi0 {
 	bus-num = <0>;
 	status = "okay";
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index 444c8da5b61..f4addca783a 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -80,8 +80,8 @@ CONFIG_NVME=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
+# CONFIG_PCIE_LAYERSCAPE_RC=y
+# CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
@@ -100,3 +100,9 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_WDT=y
 CONFIG_WDT_SBSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_TEST=y
+CONFIG_PCI_LAYERSCAPE_EP=y
+CONFIG_PCI_ENDPOINT_TEST=y

Changes to _build/rcw :

diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index e048d8b..16c1dd2 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -19,6 +19,8 @@ IRQ11_08_PMUX=1
 EVT20_PMUX=1
 EVT43_PMUX=1
 
+HOST_AGT_PEX5=1
+
 /* Drive the fan full speed pin */
 .pbi
 write 0x2320000,0x20000000

jnettlet · September 3, 2024, 8:25am

Have you verified that your kernel config has PCI endpoint functionality enabled?

CONFIG_PCI_ENDPOINT=y

CONFIG_PCI_ENDPOINT_CONFIGFS=y

CONFIG_PCI_EPF_TEST=y

rbasso · September 3, 2024, 9:09am

Yes, I double-checked the following files and they contain the kernel configs :

_build/linux/.config
_build/linux/arch/arm64/configs/defconfig

In file _build/u-boot/.config I’ve included :

CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_EP=y

jnettlet · September 3, 2024, 11:03am

can you provide your full dmesg log as an attachment. Thanks.

rbasso · September 3, 2024, 2:35pm

Here’s the dmesg log dump.
Thanks for the assistance!

dmesg_dump.txt (47.0 KB)

rbasso · September 4, 2024, 8:57am

I was able to probe the driver correctly by adding the proper IRQs into the device-tree. Now, I can see it under /sys/kernel/config/pci_ep/controllers.

Topic		Replies	Views
HoneyComb LX2 PCIe slot NXP LX2160	1	206	January 3, 2024
PCIe bifurication on the HoneyComb LX2 NXP LX2160	2	399	August 17, 2022
Honeycomb LX2 GPIOs NXP LX2160	0	5	September 9, 2024
LX2 honeycomb requires serial connection to boot, linux reboot fails NXP LX2160	5	393	January 20, 2022
USB boot on Arch linux ISO, arm-smmu errors. Board is no more booting NXP LX2160	4	231	May 5, 2022

How to set EP mode on PCIe in Honeycomb LX2?

Related Topics