eMMC error on custom carrier board

OCTEON CN9130
1

We’ve create a custom carrier board for CN9130 based on ClearFog Pro board’s schematics.
The SOM boots perfectly in base (which is the model we have for testing) and boots ubuntu with no error, but when pluggin the SOM into our carrier board, we’re getting this error related to eMMC

BootROM - 2.03
Starting AP IOROM 1.02
Booting from eMMC 0
Found valid image at boot postion 0x004
lNOTICE:  Starting binary extension
NOTICE:  SVC: DEV ID: CN913x, FREQ Mode: 0x1
ERROR:   SVC: Unsupported Frequency 0x1
w/o ecc; strap value=0
4GB capacity; strap value=0
mv_ddr: 14.0.0-gef2995c (May 30 2024 - 09:15:22)
SSCG_EN
mv_ddr: ddr freq 1 unsupported
error: mv_ddr_tdllk_get: unsupported data rate found
Synopsys DDR43 PHY Firmware version: A-2017.11
error: init_phy_pllctrl2_get: unsupported frequency found
error: init_phy_ardptrinitval_get: unsupported frequency found
error: init_phy_procodttimectl_get: unsupported frequency found
error: init_phy_caluclkinfo_get: unsupported frequency found
error: dmem_1d_2d_dram_freq_get: unsupported frequency found
error: mv_ddr_mr0_wr_get: unsupported t_wr value found
Training step/s sequence 31e failed
SNPS DDR: 1D training failed
SNPS DDR: training failed
error: mv_ddr_init failed

From a regular boot, the only parameter which changes is the FREQ Mode. In base board it’s 0x0 and in our board it is 0x1

Where does this value comes from? as SW1 and SW2 are for different purposes.

Thank you.

2

Sorry for the delays. The Freq mode is a dual purpose pin that is tied the SPI MOSI signal. I will check if it can be overridden by software if your board design conflicts with it.

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3

Thank you!
We will try to patch the board and will update you.

Cheers

4

Hello!
We’ve patched the board according to your tips but it did not work, and after double checking everything, we’ve found some missmatch in pin assignment:

  • From SOM schematics, page 2, connector J1:

    • Pin 26 is tied to GND
    • Pin 28 is tied to CP0_GPIO9_1.8V
    • Pin 30 is tied to CP0_BOOT_MODE_SEL0
    • Pin 31 is tied to CP0_BOOT_MODE_SEL1
    • …

  • From Pro Board Schematics, Page 2:

    • Pin 26 is tied to GND
    • Pin 28 is tied to B2B_BOOT_SEL_0
    • Pin 30 is tied to B2B_BOOT_SEL_1
    • Pin 31 is tied to B2B_BOOT_SEL_2

Also from your directions, there’s no CP1_MPP15 pin in SOM, there’s CP0_MPP15 tied to SPI_MOSI, which is supposed to be the pin we’re talking about right?

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Is there’s a mistake in schematics?

Also, what kind of patches should be done from u-boot in order to force the eMMC mode? Which branch from u-boot source from your repo should be used, as no one is named CN913x.

Thank you