We are currently investigating a PCIe link recovery issue observed after a host soft reboot on a SolidRun ClearFog platform based on the NXP LX2 SoC, and we would appreciate your support with a host-side validation experiment.
As part of our investigation, we captured warm reboot traces using a LeCroy PCIe analyzer and analyzed the PERST# timing during the reboot sequence.
We observed the following:
- SolidRun ClearFog / NXP LX2: PERST# is de-asserted approximately 53 ms after assertion.
- X12 reference server: PERST# is de-asserted approximately 220 ms after assertion.
We also observed that FULL_RESET_COMPLETE is asserted on the X12 platform during reboot, whereas it remains de-asserted on the ClearFog LX2 platform following a host soft reboot.
Based on these observations, one hypothesis we would like to validate is whether the shorter PERST# assertion duration on the ClearFog LX2 platform provides sufficient time for the PCIe endpoint device to complete its internal reset sequence before PCIe link retraining begins.
Below logs from the soft reboot failure scenario:
// Device ID and Vendor ID was fetched from Configuration Read
[ 3.092036] pci 0001:00:00.0: [1957:8d80] type 01 class 0x060400
[ 3.092106] pci 0001:00:00.0: supports D1 D2
[ 3.092109] pci 0001:00:00.0: PME# supported from D0 D1 D2 D3hot
[ 3.093081] pci 0001:01:00.0: [17cb:0601] type 00 class 0x120000
[ 3.093184] pci 0001:01:00.0: reg 0x10: [mem 0xa040000000-0xa040000fff 64bit]
[ 3.093251] pci 0001:01:00.0: reg 0x18: [mem 0xa040008000-0xa04000ffff 64bit]
[ 3.094084] pci 0001:01:00.0: PME# supported from D0 D3hot D3cold
[ 3.094307] pci 0001:01:00.0: reg 0x224: [mem 0x00000000-0x00000fff 64bit]
[ 3.094309] pci 0001:01:00.0: VF(n) BAR0 space: [mem 0x00000000-0x0000ffff 64bit] (contains BAR0 for 16 VFs)
[ 3.094376] pci 0001:01:00.0: reg 0x22c: [mem 0x00000000-0x00007fff 64bit]
[ 3.094379] pci 0001:01:00.0: VF(n) BAR2 space: [mem 0x00000000-0x0007ffff 64bit] (contains BAR2 for 16 VFs)
// PCIe link up to Gen3
[ 3.095106] pci 0001:01:00.0: 63.008 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x8 link at 0001:00:00.0 (capable of 252.048 Gb/s with 16.0 GT/s PCIe x16 link)
[ 3.095864] pci 0001:00:00.0: BAR 14: assigned [mem 0xa040000000-0xa0400fffff]
[ 3.095871] pci 0001:01:00.0: BAR 2: assigned [mem 0xa040000000-0xa040007fff 64bit]
[ 3.095924] pci 0001:01:00.0: BAR 9: assigned [mem 0xa040008000-0xa040087fff 64bit]
[ 3.095949] pci 0001:01:00.0: BAR 0: assigned [mem 0xa040088000-0xa040088fff 64bit]
[ 3.096002] pci 0001:01:00.0: BAR 7: assigned [mem 0xa040089000-0xa040098fff 64bit]
[ 3.096026] pci 0001:00:00.0: PCI bridge to [bus 01-ff]
[ 3.096031] pci 0001:00:00.0: bridge window [mem 0xa040000000-0xa0400fffff]
[ 3.096045] pci 0001:00:00.0: Max Payload Size set to 256/ 256 (was 128), Max Read Rq 256
[ 3.096119] pci 0001:01:00.0: Max Payload Size set to 256/ 512 (was 128), Max Read Rq 256
[ 3.119400] pci-endpoint-test 0000:00:00.0: Adding to iommu group 0
[ 3.119514] pci-endpoint-test 0001:00:00.0: Adding to iommu group 1
[ 3.138132] ehci-pci: EHCI PCI platform driver
[ 3.138280] ohci-pci: OHCI PCI platform driver
[ 3.982887] pcieport 0000:00:00.0: PME: Signaling with IRQ 45
[ 3.983105] pcieport 0001:00:00.0: PME: Signaling with IRQ 46
[ 7.555535] mhi-pci-generic 0001:01:00.0: Adding to iommu group 11
// BAR resource was assigned via PCIe MMIO
[ 7.531922] mhi: loading out-of-tree module taints kernel.
[ 7.548572] CSM-DP: Register MHI driver!
[ 7.555583] mhi-pci-generic 0001:01:00.0: BAR 0: assigned [mem 0xa040088000-0xa040088fff 64bit]
[ 7.555677] mhi-pci-generic 0001:01:00.0: enabling device (0000 → 0002)
[ 7.601184] mhi mhi0: Requested to power ON
// mhi-host saw device MHi state is SYS_ERR, but it should be RESET
[ 7.601192] mhi mhi0: Attempting power ON with EE: PRIMARY BOOTLOADER, state: SYS ERROR
[ 180.500646] mhi mhi0: Failed to reset MHI due to syserr state
[ 180.500655] mhi-pci-generic 0001:01:00.0: failed to power up MHI controller
[ 180.524705] mhi-pci-generic: probe of 0001:01:00.0 failed with error -110
Thanks for your help!
BR,
Yash