# SERDES configuration for Honeycomb LX2160A

**URL:** <https://community.solid-run.com/t/serdes-configuration-for-honeycomb-lx2160a/173>\
**Category:** NXP LX2160\
**Created:** [September 24, 2021, 1:43pm UTC](https://community.solid-run.com/t/serdes-configuration-for-honeycomb-lx2160a/173 "2021-09-24T13:43:30Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![Nick](https://avatars.discourse-cdn.com/v4/letter/n/f9ae1b/32.png) [@Nick](https://community.solid-run.com/u/Nick)\
**Post date:** [September 24, 2021, 1:43pm UTC](https://community.solid-run.com/t/serdes-configuration-for-honeycomb-lx2160a/173/1 "2021-09-24T13:43:30Z")

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Poking around a bunch but haven’t found a clear answer to this one so figured I would ask the ether.

The default initialization images have a SERDES configuration of 8\_5\_2. SD3 protocol 2 means than PCIe controller 5 and 6 are x4 lanes but the Honeycomb carrier board has an x8 link, the block diagram shows all 8 lanes of SD3 connected. Should the init image for this board utilize SD3 protocol 1?

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**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [September 24, 2021, 3:38pm UTC](https://community.solid-run.com/t/serdes-configuration-for-honeycomb-lx2160a/173/2 "2021-09-24T15:38:28Z")

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As you can see in the NXP LX2160A reference manual SERDES configuration 2 on SD3 is for the x8 PCIe lanes. SERDES configuration 3 is for the 2 x x4 ports, and you can see it is used for our lx2160a\_uefi images that are built to support PCIe bifurcation.

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**Author:** ![Nick](https://avatars.discourse-cdn.com/v4/letter/n/f9ae1b/32.png) [@Nick](https://community.solid-run.com/u/Nick)\
**Post date:** [September 24, 2021, 4:12pm UTC](https://community.solid-run.com/t/serdes-configuration-for-honeycomb-lx2160a/173/3 "2021-09-24T16:12:37Z")

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Thank you for the quick answer!

Is the information provided here incorrect then?

> **[Com Express Type 7 LX2160A - SolidRun](https://developer.solid-run.com/knowledge-base/lx2160a-cex7-user-manual/#serdes-block-3-sd3-pllf-plls-100mhz-spread-spectrum-disabled)**
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> Revisions and Notes  Date Owner Revision Notes — — — Pre-released information Introduction This document is intended for hardware engineers that are willing to integrate LX2160A COM express type 7 module from SolidRun ltd. The document provides...

It says SD3 protocol 0 is OFF, 1 is x8, and 2 is x4/x4

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<div class="post-metadata">

**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [September 25, 2021, 6:33am UTC](https://community.solid-run.com/t/serdes-configuration-for-honeycomb-lx2160a/173/4 "2021-09-25T06:33:09Z")

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Yes, I will have it updated. In general if there are any questions please cross reference the NXP reference manual. It is freely available with registration.

 ![Screenshot from 2021-09-25 08-31-40](https://europe1.discourse-cdn.com/flex005/uploads/solid_run/original/1X/442ad922ac6f8a60ff0d28e9c9d7876a6bdf172a.png)

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<div class="post-metadata">

**Author:** ![Nick](https://avatars.discourse-cdn.com/v4/letter/n/f9ae1b/32.png) [@Nick](https://community.solid-run.com/u/Nick)\
**Post date:** [September 25, 2021, 12:50pm UTC](https://community.solid-run.com/t/serdes-configuration-for-honeycomb-lx2160a/173/5 "2021-09-25T12:50:23Z")

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Thank you again so much!