# Pin details

**URL:** https://community.solid-run.com/t/pin-details/390
**Category:** OCTEON CN9130
**Created:** [July 15, 2022, 7:02am UTC](https://community.solid-run.com/t/pin-details/390 "2022-07-15T07:02:41Z")
**Posts on this page:** 4
**Page:** 1

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### Author: ![sanjeevini](https://avatars.discourse-cdn.com/v4/letter/s/c6cbf5/32.png) [@sanjeevini](https://community.solid-run.com/u/sanjeevini)
#### Post date: [July 15, 2022, 7:02am UTC](https://community.solid-run.com/t/pin-details/390/1 "2022-07-15T07:02:41Z")

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i am using this module please provide the pin details which will help us to design

mainly 1)how to reset this module 2) i need to connect the RJ-45 connector to CN9130 ethernet PHY so KIndly Provide the pin details

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### Author: ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)
#### Post date: [July 15, 2022, 7:21am UTC](https://community.solid-run.com/t/pin-details/390/2 "2022-07-15T07:21:22Z")

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All information including simple schematics are available here, [https://solidrun.atlassian.net/wiki/spaces/developer/pages/197493875/CN9130+SOM+Hardware+User+Manual](https://solidrun.atlassian.net/wiki/spaces/developer/pages/197493875/CN9130+SOM+Hardware+User+Manual)

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### Author: ![sanjeevini](https://avatars.discourse-cdn.com/v4/letter/s/c6cbf5/32.png) [@sanjeevini](https://community.solid-run.com/u/sanjeevini)
#### Post date: [July 15, 2022, 11:30am UTC](https://community.solid-run.com/t/pin-details/390/3 "2022-07-15T11:30:28Z")

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hi i want reset the CN9130 Module and reset PHY …in pin details i am seeing so many RESET pin given so please help me

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### Author: ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)
#### Post date: [July 15, 2022, 12:01pm UTC](https://community.solid-run.com/t/pin-details/390/4 "2022-07-15T12:01:47Z")

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If you download the simplified schematic for the SOM you can see that the 1GB phy reset is connected to CP0\_SYSRST\_IN\_N and the RESET circuit is connected to CP0\_SYSRST\_OUT\_N which then provides, CP0\_SYSRST\_IN\_N
