# LX2160A second RCW source

**URL:** <https://community.solid-run.com/t/lx2160a-second-rcw-source/431>\
**Category:** NXP LX2160\
**Created:** [August 20, 2022, 3:45am UTC](https://community.solid-run.com/t/lx2160a-second-rcw-source/431 "2022-08-20T03:45:26Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![dstepanov](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/dstepanov/32/144_2.png) [@dstepanov](https://community.solid-run.com/u/dstepanov)\
**Post date:** [August 20, 2022, 3:45am UTC](https://community.solid-run.com/t/lx2160a-second-rcw-source/431/1 "2022-08-20T03:45:26Z")

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Hello! I’m using LX2160A clearfog development board and trying to implement reliable boot in case of failure of one of the boot sources (eMMC/SD/SPI).

LX2160A Reference Manual (Rev. 0RH, 07/2020) in detailed Power-On reset description (4.9.5, table 11, stage 13) points that it is possible to use second RCW source

> If the Service processor detects that the RCW loading failed, it initiates RCW loading from a second RCW source. If boot fails from the RCW loaded at offset 0 or 0x1000 (in case of SD), the boot ROM searches for RCW at 8 MB (8 MB + 0x1000 for SD) offset on the device.

I’m little bit confused with this description - what really happens if boot fails? where the second RCW source is selected? Does the boot process try to read RCW from first boot source (using 2 offsets) and if these 2 attempts fails it performs another 2 attempts (with 2 different offsets)?

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**Author:** ![dstepanov](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/dstepanov/32/144_2.png) [@dstepanov](https://community.solid-run.com/u/dstepanov)\
**Post date:** [August 21, 2022, 1:07pm UTC](https://community.solid-run.com/t/lx2160a-second-rcw-source/431/2 "2022-08-21T13:07:50Z")

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Created [LX2160A second RCW source - NXP Community](https://community.nxp.com/t5/Layerscape/LX2160A-second-RCW-source/m-p/1509056#M11056) as it its more NXP specific topic

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**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [August 22, 2022, 5:49am UTC](https://community.solid-run.com/t/lx2160a-second-rcw-source/431/3 "2022-08-22T05:49:00Z")

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If you don’t get a reply in a reasonable amount of time ping this thread and I will try and follow up with NXP.

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**Author:** ![dstepanov](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/dstepanov/32/144_2.png) [@dstepanov](https://community.solid-run.com/u/dstepanov)\
**Post date:** [September 9, 2022, 8:09am UTC](https://community.solid-run.com/t/lx2160a-second-rcw-source/431/4 "2022-09-09T08:09:07Z")

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Looks like it’s time to ping this thread since i haven’t got any reply on NXP forum

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**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [September 9, 2022, 8:10am UTC](https://community.solid-run.com/t/lx2160a-second-rcw-source/431/5 "2022-09-09T08:10:52Z")

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okay, I will try to track down NXP on this.