# iMx8M Plus external RAM inline ECC feature

**URL:** <https://community.solid-run.com/t/imx8m-plus-external-ram-inline-ecc-feature/196>\
**Category:** NXP i.MX8M Plus\
**Tags:** iMX8M-plus\
**Created:** [November 23, 2021, 6:33pm UTC](https://community.solid-run.com/t/imx8m-plus-external-ram-inline-ecc-feature/196 "2021-11-23T18:33:29Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![ldesa](https://avatars.discourse-cdn.com/v4/letter/l/71e660/32.png) [@ldesa](https://community.solid-run.com/u/ldesa)\
**Post date:** [November 23, 2021, 6:33pm UTC](https://community.solid-run.com/t/imx8m-plus-external-ram-inline-ecc-feature/196/1 "2021-11-23T18:33:29Z")

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Has anyone played with iMx8M Plus external RAM inline ECC feature?  
May you share your findings about it? Like bandwidth impact, power impact, good hints to know.

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**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [November 24, 2021, 11:07am UTC](https://community.solid-run.com/t/imx8m-plus-external-ram-inline-ecc-feature/196/2 "2021-11-24T11:07:46Z")

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I am still working on a solid implementation. This is something that NXP is still validating, so I am working in parallel to provide some bandwidth and validation documentation.