# i.MX8MP second ethernet

**URL:** <https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054>\
**Category:** NXP i.MX8M Plus\
**Tags:** iMX8M-plus\
**Created:** [August 4, 2025, 12:22pm UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054 "2025-08-04T12:22:23Z")\
**Posts on this page:** 15\
**Page:** 1

<div class="post-metadata">

**Author:** ![RadU-Callum](https://avatars.discourse-cdn.com/v4/letter/r/51bf81/32.png) [@RadU-Callum](https://community.solid-run.com/u/RadU-Callum)\
**Post date:** [August 4, 2025, 12:22pm UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/1 "2025-08-04T12:22:23Z")

</div>

Hello,

I am currently working with the i.MX8M Plus SOM. I see that the SOM supports two Giga Ethernet interfaces. There is a note attached to this page that says “Please note that default SOM configuration includes only 1 PHY. For 2nd PHY option please contact us for details.”

> **[i.MX8M Plus SOM Hardware User Manual - Developer Center -  SolidRun](https://solidrun.atlassian.net/wiki/spaces/developer/pages/197493766/i.MX8M+Plus+SOM+Hardware+User+Manual)**

I have had an attempt to include this interface by patching the imx8mp-hummingboard-pulse.dtsi to include the fec driver for the second ethernet:

```auto
&fec {
	status = "okay";
};

```

This change to the device tree seems to bring up the second Ethernet, but I am unable to get connection to this new interface. I believe this might be because the physical connections from the SOM to my Ethernet are incorrect.

After chasing the fec in the device tree, imx8mp-sr-som.dtsi, I see that the pinctrl\_fec is defined as:

```auto
	pinctrl_fec: fecgrp {
		fsl,pins = <
                        MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
                        MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
                        MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
                        MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
                        MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
                        MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
                        MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
                        MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
                        MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
                        MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
                        MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
                        MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
                        MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
                        MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
		>;
	};

	pinctrl_phy1: phy1grp {
		fsl,pins = <
			/* INT_N: weak i/o, pull-up */
			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140
			/* RESET_N: weak i/o, open drain, external 10k pull-up */
			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x20
		>;
	};

```

I currently have my ethernet cable connected directly to SAI1\_RXD2, SAI1\_RXD3, SAI1\_RXD0, SAI1\_RXD1, which correspond to pins 71, 74, 78, 80 on connector J7, in the schematic: [Attachments - i.MX8M Plus SOM Hardware User Manual - Developer Center - &nbsp;SolidRun](https://developer.resources.solid-run.com/wiki/pages/viewpageattachments.action?pageId=197493766&preview=%2F197493766%2F287211733%2Fi.MX8M%20Plus%20SOM%20Simplified%20Schematics%20Rev%201.1.pdf)

Please could you let me know if my current setup is correct, or if there is something I have missed.

Many thanks!

---

<div class="post-metadata">

**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [August 5, 2025, 5:14am UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/2 "2025-08-05T05:14:36Z")

</div>

That note was for the first revision of the SOM. Since then we are assembling most iMX8MP SOMs with dual ethernet phys as the default. I will review your pin settings, but can you please upload your dmesg output for me to review?

---

<div class="post-metadata">

**Author:** ![RadU-Callum](https://avatars.discourse-cdn.com/v4/letter/r/51bf81/32.png) [@RadU-Callum](https://community.solid-run.com/u/RadU-Callum)\
**Post date:** [August 5, 2025, 8:23am UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/3 "2025-08-05T08:23:25Z")

</div>

Thanks, this is what I get from dmesg:

[0.000000] psci: probing for conduit method from DT.  
[1.310585] igb: Intel(R) Gigabit Ethernet Network Driver  
[1.615836] optee: probing for conduit method.  
[1.821594] Bluetooth: BNEP (Ethernet Emulation) ver 1.3  
[2.114147] fec 30be0000.ethernet eth0: registered PHC device 0  
[6.403623] imx-dwmac 30bf0000.ethernet: IRQ eth\_lpi not found  
[6.454831] imx-dwmac 30bf0000.ethernet: force\_sf\_dma\_mode is ignored if force\_thresh\_dma\_mode is set.  
[6.484261] imx-dwmac 30bf0000.ethernet: User ID: 0x10, Synopsys ID: 0x51  
[6.484277] imx-dwmac 30bf0000.ethernet: DWMAC4/5  
[6.497598] imx-dwmac 30bf0000.ethernet: DMA HW capability register supported  
[6.507226] imx-dwmac 30bf0000.ethernet: RX Checksum Offload Engine supported  
[6.524088] imx-dwmac 30bf0000.ethernet: Wake-Up On Lan supported  
[6.570036] imx-dwmac 30bf0000.ethernet: Enable RX Mitigation via HW Watchdog Timer  
[6.580405] imx-dwmac 30bf0000.ethernet: Enabled L3L4 Flow TC (entries=8)  
[6.593674] imx-dwmac 30bf0000.ethernet: Enabled RFS Flow TC (entries=8)  
[6.603411] imx-dwmac 30bf0000.ethernet: Enabling HW TC (entries=256, max\_off=256)  
[6.613031] imx-dwmac 30bf0000.ethernet: Using 34 bits DMA width  
[7.307471] imx-dwmac 30bf0000.ethernet eth1: PHY [stmmac-0:00] driver [ADIN1300] (irq=195)  
[7.329014] imx-dwmac 30bf0000.ethernet eth1: Register MEM\_TYPE\_PAGE\_POOL RxQ-0  
[7.336848] imx-dwmac 30bf0000.ethernet eth1: Register MEM\_TYPE\_PAGE\_POOL RxQ-1  
[7.349673] imx-dwmac 30bf0000.ethernet eth1: Register MEM\_TYPE\_PAGE\_POOL RxQ-2  
[7.359797] imx-dwmac 30bf0000.ethernet eth1: Register MEM\_TYPE\_PAGE\_POOL RxQ-3  
[7.376275] imx-dwmac 30bf0000.ethernet eth1: Register MEM\_TYPE\_PAGE\_POOL RxQ-4  
[7.405307] imx-dwmac 30bf0000.ethernet eth1: No Safety Features support found  
[7.412986] imx-dwmac 30bf0000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported  
[7.425906] imx-dwmac 30bf0000.ethernet eth1: registered PTP clock  
[7.434162] imx-dwmac 30bf0000.ethernet eth1: FPE workqueue start  
[7.440379] imx-dwmac 30bf0000.ethernet eth1: configuring for phy/rgmii-id link mode  
[7.450464] 8021q: adding VLAN 0 to HW filter on device eth1  
[7.466865] Generic PHY 30be0000.ethernet-1:01: attached PHY driver (mii\_bus:phy\_addr=30be0000.ethernet-1:01, irq=POLL)  
[7.480574] fec 30be0000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx  
[7.809768] IPv6: ADDRCONF(NETDEV\_CHANGE): eth0: link becomes ready  
[10.047856] imx-dwmac 30bf0000.ethernet eth1: Link is Up - 100Mbps/Full - flow control rx/tx  
[10.056353] IPv6: ADDRCONF(NETDEV\_CHANGE): eth1: link becomes ready

From imx8mp.dtsi I see that fec: ethernet@30be0000 and eqos: ethernet@30bf0000, so it seems that the fec drives eth0 which is the one I can’t get working, and eth1 works fine.

Best regards

---

<div class="post-metadata">

**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [August 5, 2025, 9:54am UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/4 "2025-08-05T09:54:03Z")

</div>

and which BSP are you using?

---

<div class="post-metadata">

**Author:** ![RadU-Callum](https://avatars.discourse-cdn.com/v4/letter/r/51bf81/32.png) [@RadU-Callum](https://community.solid-run.com/u/RadU-Callum)\
**Post date:** [August 5, 2025, 9:59am UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/5 "2025-08-05T09:59:45Z")

</div>

I’m using the meta-solidrun-arm-imx8 BSP, which i got from following the kirkstone build guide: [GitHub - SolidRun/meta-solidrun-arm-imx8 at kirkstone-imx8m](https://github.com/SolidRun/meta-solidrun-arm-imx8/tree/kirkstone-imx8m)

---

<div class="post-metadata">

**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [August 6, 2025, 8:09am UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/6 "2025-08-06T08:09:50Z")

</div>

can you provide your SKU and/or Serial Number so I can verify your SOM does in fact have dual phy’s assembled on it?

---

<div class="post-metadata">

**Author:** ![RadU-Callum](https://avatars.discourse-cdn.com/v4/letter/r/51bf81/32.png) [@RadU-Callum](https://community.solid-run.com/u/RadU-Callum)\
**Post date:** [August 6, 2025, 9:10am UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/7 "2025-08-06T09:10:34Z")

</div>

On the physical SOM i can see that i am using the IMX8MPLUS SOM v1.2

Serial number:

root@imx8mpsolidrun:~# cat /sys/devices/soc0/serial\_number  
0E0AB800FE02828C

---

<div class="post-metadata">

**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [August 7, 2025, 10:20am UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/8 "2025-08-07T10:20:05Z")

</div>

can you boot into the u-boot console and use the tlv\_eeprom command to dump your SKU. That serial number is for the SOC on the SOM and not the SOM itself. The SKU will provide the information to know if your SOM has both phy’s populated.

---

<div class="post-metadata">

**Author:** ![RadU-Callum](https://avatars.discourse-cdn.com/v4/letter/r/51bf81/32.png) [@RadU-Callum](https://community.solid-run.com/u/RadU-Callum)\
**Post date:** [August 7, 2025, 10:50am UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/9 "2025-08-07T10:50:33Z")

</div>

u-boot=\> tlv\_eeprom  
TLV: 0  
TlvInfo Header:  
Id String: TlvInfo  
Version: 1  
Total Length: 150  
TLV Name Code Len Value

* * *

Product Name 0x21 28 i.MX8M Plus System on Module  
Part Number 0x22 23 SRMP8QDWB1D04GE008V12C0  
Serial Number 0x23 16 IP00257241900002  
Base MAC Address 0x24 6 D0:63:B4:05:D2:E1  
Manufacture Date 0x25 19 2024-05-08 05:38:27  
Device Version 0x26 1 18  
Label Revision 0x27 1 1  
Platform Name 0x28 11 i.MX8M Plus  
MAC Addresses 0x2A 2 2  
Manufacturer 0x2B 3 IMI  
Country Code 0x2C 2 PH  
Vendor Name 0x2D 8 SolidRun  
CRC-32 0xFE 4 0xA4C57A05  
Checksum is valid.

many thanks

---

<div class="post-metadata">

**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [August 7, 2025, 3:37pm UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/10 "2025-08-07T15:37:43Z")

</div>

Okay, that explains it. That SOM only has a single phy assembled. It would have 2PH at the end if it was a dual phy.

---

<div class="post-metadata">

**Author:** ![RadU-Callum](https://avatars.discourse-cdn.com/v4/letter/r/51bf81/32.png) [@RadU-Callum](https://community.solid-run.com/u/RadU-Callum)\
**Post date:** [August 8, 2025, 8:56am UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/11 "2025-08-08T08:56:43Z")

</div>

Would it be possible to fit a second PHY on the SOM, or even on a carrier card that would allow for this second Ethernet?

If it is possible to fit a PHY on a carrier card what pins from the SOM should I connect to?

Since there is no PHY, then are pins 72, 74, 78, 80, on connector J7, connected to the processor at all, or are they dead connections?

---

<div class="post-metadata">

**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [August 8, 2025, 11:13am UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/12 "2025-08-08T11:13:43Z")

</div>

We have an assembly option that fits 2 phys to the SOM, This is available on newer SOMs that are shipped with the HB Pulse AI, and HB IIoT. If you want you can assemble the phy yourself. You can not assemble the PHY to the carrier as the pins are not brought out if the phy is not assembled.

---

<div class="post-metadata">

**Author:** ![RadU-Callum](https://avatars.discourse-cdn.com/v4/letter/r/51bf81/32.png) [@RadU-Callum](https://community.solid-run.com/u/RadU-Callum)\
**Post date:** [August 8, 2025, 12:51pm UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/13 "2025-08-08T12:51:25Z")

</div>

Thank you, this is very helpful.

I can see the footprint for a chip on the SOM that is not fitted (U13) can you confirm if this is the footprint for the second PHY.

I can see that the PHY that is fitted is a adin1300bcpz, would this be the chip I need to assemble the second PHY?

Many thanks

---

<div class="post-metadata">

**Author:** ![RadU-Callum](https://avatars.discourse-cdn.com/v4/letter/r/51bf81/32.png) [@RadU-Callum](https://community.solid-run.com/u/RadU-Callum)\
**Post date:** [August 8, 2025, 1:01pm UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/14 "2025-08-08T13:01:01Z")

</div>

Would it be possible to send me a schematic with the second PHY fitted?

---

<div class="post-metadata">

**Author:** ![RadU-Callum](https://avatars.discourse-cdn.com/v4/letter/r/51bf81/32.png) [@RadU-Callum](https://community.solid-run.com/u/RadU-Callum)\
**Post date:** [October 3, 2025, 4:25pm UTC](https://community.solid-run.com/t/i-mx8mp-second-ethernet/1054/15 "2025-10-03T16:25:53Z")

</div>

Hello,

I have now bought some more i.MX8M Plus SOMs, which have the second PHY fitted.

```auto
u-boot=> tlv_eeprom                                                             
TLV: 0                                                                          
TlvInfo Header:                                                                 
   Id String: TlvInfo                                                        
   Version: 1                                                              
   Total Length: 150                                                            
TLV Name Code Len Value                                             
-------------------- ---- --- -----                                             
Product Name 0x21 28 i.MX8M Plus System on Module                      
Part Number 0x22 23 SRMP8QDWB1D04GE008V12C2                           
Serial Number 0x23 16 IP10396253900059                                  
Base MAC Address 0x24 6 D0:63:B4:06:DE:9D                                 
Manufacture Date 0x25 19 09/27/2025 07:10:53                               
Device Version 0x26 1 18                                                
Label Revision 0x27 1 1                                                 
Platform Name 0x28 11 i.MX8M Plus                                       
MAC Addresses 0x2A 2 2                                                 
Manufacturer 0x2B 3 IMI                                               
Country Code 0x2C 2 PH                                                
Vendor Name 0x2D 8 SolidRun                                          
CRC-32 0xFE 4 0x223C48CE                                        
Checksum is valid.    

```

I have tested the new SOM with the original default kirkstone image as well as an image where I set,

```auto
&fec {
  status = “okay”;
};

```

However I have been unsuccessful in getting Ethernet connection.

Any assistance on configuring the device tree to get Ethernet working would be greatly appreciated.

Thanks