# FPGA missing on PCIE tree **URL:** \ **Category:** Uncategorized\ **Created:** [July 28, 2023, 2:15pm UTC](https://community.solid-run.com/t/fpga-missing-on-pcie-tree/691 "2023-07-28T14:15:23Z")\ **Posts on this page:** 7\ **Page:** 1
**Author:** ![ChuandeChen](https://avatars.discourse-cdn.com/v4/letter/c/ecae2f/32.png) [@ChuandeChen](https://community.solid-run.com/u/ChuandeChen)\ **Post date:** [July 28, 2023, 2:15pm UTC](https://community.solid-run.com/t/fpga-missing-on-pcie-tree/691/1 "2023-07-28T14:15:23Z")
My topo is Solidrun type 7 CPU —\> PEX8714 —\> FPGA. I cannot find out the FPGA from PCIE tree. Could some one help? ---
**Author:** ![ChuandeChen](https://avatars.discourse-cdn.com/v4/letter/c/ecae2f/32.png) [@ChuandeChen](https://community.solid-run.com/u/ChuandeChen)\ **Post date:** [July 28, 2023, 2:17pm UTC](https://community.solid-run.com/t/fpga-missing-on-pcie-tree/691/2 "2023-07-28T14:17:27Z")
pcie rescan doesn’t help. suppose need some patch. ---
**Author:** ![ChuandeChen](https://avatars.discourse-cdn.com/v4/letter/c/ecae2f/32.png) [@ChuandeChen](https://community.solid-run.com/u/ChuandeChen)\ **Post date:** [July 28, 2023, 2:30pm UTC](https://community.solid-run.com/t/fpga-missing-on-pcie-tree/691/3 "2023-07-28T14:30:12Z")
looks PEX8714 PCIE config space is write disabled by default at boot. how to enable it by default at boot? ---
**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\ **Post date:** [July 29, 2023, 4:59am UTC](https://community.solid-run.com/t/fpga-missing-on-pcie-tree/691/4 "2023-07-29T04:59:52Z")
Please post the output of dmesg. There should be nothing specific to the LX2160a PCIe host bridge that would enable / disable RO config space on the switch. ---
**Author:** ![ChuandeChen](https://avatars.discourse-cdn.com/v4/letter/c/ecae2f/32.png) [@ChuandeChen](https://community.solid-run.com/u/ChuandeChen)\ **Post date:** [July 29, 2023, 9:06am UTC](https://community.solid-run.com/t/fpga-missing-on-pcie-tree/691/5 "2023-07-29T09:06:09Z")
Hi jnettlet, Thanks very much! here is the dmesg log. [2.618427] layerscape-pcie 3600000.pcie: host bridge /soc/pcie@3600000 ranges: [2.625746] layerscape-pcie 3600000.pcie: MEM 0x9400000000…0x97ffffffff → 0xa400000000 [2.634268] layerscape-pcie 3600000.pcie: MEM 0x9040000000…0x90ffffffff → 0x0040000000 [2.642787] layerscape-pcie 3600000.pcie: IO 0x9010000000…0x901000ffff → 0x0000000000 [2.651391] layerscape-pcie 3600000.pcie: PCI host bridge to bus 0000:00 [2.658085] pci\_bus 0000:00: root bus resource [bus 00-ff] [2.663563] pci\_bus 0000:00: root bus resource [mem 0x9400000000-0x97ffffffff pref] (bus address [0xa400000000-0xa7ffffffff]) [2.674856] pci\_bus 0000:00: root bus resource [mem 0x9040000000-0x90ffffffff] (bus address [0x40000000-0xffffffff]) [2.685367] pci\_bus 0000:00: root bus resource [io 0x0000-0xffff] [2.691558] pci 0000:00:00.0: [1957:8d80] type 01 class 0x060400 [2.697617] pci 0000:00:00.0: supports D1 D2 [2.701878] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot [2.708943] pci 0000:01:00.0: [10b5:8714] type 01 class 0x060400 [2.715084] pci 0000:01:00.0: reg 0x10: [mem 0x9040000000-0x904003ffff] [2.722911] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold [2.729572] pci 0000:01:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x4 link at 0000:00:00.0 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link) [2.745892] pci 0000:02:01.0: [10b5:8714] type 01 class 0x060400 [2.753290] pci 0000:02:01.0: PME# supported from D0 D3hot D3cold [2.760230] pci 0000:02:02.0: [10b5:8714] type 01 class 0x060400 [2.767622] pci 0000:02:02.0: PME# supported from D0 D3hot D3cold [2.774572] pci 0000:02:03.0: [10b5:8714] type 01 class 0x060400 [2.781965] pci 0000:02:03.0: PME# supported from D0 D3hot D3cold [2.788929] pci 0000:02:04.0: [10b5:8714] type 01 class 0x060400 [2.796320] pci 0000:02:04.0: PME# supported from D0 D3hot D3cold [2.804155] pci\_bus 0000:03: busn\_res: can not insert [bus 03] under [bus 02] (conflicts with (null) [bus 02]) [2.814805] pci 0000:02:01.0: devices behind bridge are unusable because [bus 03] cannot be assigned for them [2.824994] pci\_bus 0000:04: busn\_res: can not insert [bus 04] under [bus 02] (conflicts with (null) [bus 02]) [2.835645] pci 0000:02:02.0: devices behind bridge are unusable because [bus 04] cannot be assigned for them [2.845832] pci\_bus 0000:05: busn\_res: can not insert [bus 05] under [bus 02] (conflicts with (null) [bus 02]) [2.856485] pci 0000:02:03.0: devices behind bridge are unusable because [bus 05] cannot be assigned for them [2.866673] pci\_bus 0000:06: busn\_res: can not insert [bus 06] under [bus 02] (conflicts with (null) [bus 02]) [2.877322] pci 0000:02:04.0: devices behind bridge are unusable because [bus 06] cannot be assigned for them [2.887411] pci 0000:01:00.0: bridge has subordinate 02 but max busn 06 [2.894086] pci 0000:00:00.0: BAR 14: assigned [mem 0x9040000000-0x90400fffff] [2.901317] pci 0000:01:00.0: BAR 0: assigned [mem 0x9040000000-0x904003ffff] [2.908470] pci 0000:02:01.0: PCI bridge to [bus 03] [2.913524] pci 0000:02:02.0: PCI bridge to [bus 04] [2.918577] pci 0000:02:03.0: PCI bridge to [bus 05] [2.923631] pci 0000:02:04.0: PCI bridge to [bus 06] [2.928684] pci 0000:01:00.0: PCI bridge to [bus 02] [2.933737] pci 0000:00:00.0: PCI bridge to [bus 01-ff] [2.938956] pci 0000:00:00.0: bridge window [mem 0x9040000000-0x90400fffff] [2.946093] pci 0000:00:00.0: Max Payload Size set to 256/ 256 (was 128), Max Read Rq 256 [2.954630] pci 0000:01:00.0: Max Payload Size set to 256/ 256 (was 128), Max Read Rq 128 [2.963178] pci 0000:02:01.0: Max Payload Size set to 256/ 256 (was 128), Max Read Rq 128 [2.971725] pci 0000:02:02.0: Max Payload Size set to 256/ 256 (was 128), Max Read Rq 128 [2.980274] pci 0000:02:03.0: Max Payload Size set to 256/ 256 (was 128), Max Read Rq 128 [2.988822] pci 0000:02:04.0: Max Payload Size set to 256/ 256 (was 128), Max Read Rq 128 [2.997454] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges: [3.004778] layerscape-pcie 3800000.pcie: MEM 0xa400000000…0xa7ffffffff → 0xa400000000 [3.013309] layerscape-pcie 3800000.pcie: MEM 0xa040000000…0xa0ffffffff → 0x0040000000 [3.021829] layerscape-pcie 3800000.pcie: IO 0xa010000000…0xa01000ffff → 0x0000000000 [3.030427] layerscape-pcie 3800000.pcie: PCI host bridge to bus 0001:00 [3.037122] pci\_bus 0001:00: root bus resource [bus 00-ff] [3.042600] pci\_bus 0001:00: root bus resource [mem 0xa400000000-0xa7ffffffff pref] [3.050249] pci\_bus 0001:00: root bus resource [mem 0xa040000000-0xa0ffffffff] (bus address [0x40000000-0xffffffff]) [3.060761] pci\_bus 0001:00: root bus resource [io 0x10000-0x1ffff] (bus address [0x0000-0xffff]) [3.069725] pci 0001:00:00.0: [1957:8d80] type 01 class 0x060400 [3.075796] pci 0001:00:00.0: supports D1 D2 [3.080058] pci 0001:00:00.0: PME# supported from D0 D1 D2 D3hot [3.087483] pci 0001:00:00.0: PCI bridge to [bus 01-ff] [3.092718] pci 0001:00:00.0: Max Payload Size set to 256/ 256 (was 128), Max Read Rq 256 ---
**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\ **Post date:** [July 29, 2023, 11:51am UTC](https://community.solid-run.com/t/fpga-missing-on-pcie-tree/691/6 "2023-07-29T11:51:07Z")
This issue was fixed in mainline u-boot but is still not backported to NXP’s BSP. [pci: Update the highest subordinate bus number for bridge setup (19e1b8d9) · Commits · U-Boot / U-Boot · GitLab](https://source.denx.de/u-boot/u-boot/-/commit/19e1b8d9b283514eb6ab8d7253f4867068007938) Additionally there is a bug that I debugged in another thread that needs to be patched in our device-tree. [Pci kernel panic when upgrading to latest - #12 by jnettlet](https://community.solid-run.com/t/pci-kernel-panic-when-upgrading-to-latest/679/12) ---
**Author:** ![ChuandeChen](https://avatars.discourse-cdn.com/v4/letter/c/ecae2f/32.png) [@ChuandeChen](https://community.solid-run.com/u/ChuandeChen)\ **Post date:** [July 29, 2023, 1:01pm UTC](https://community.solid-run.com/t/fpga-missing-on-pcie-tree/691/7 "2023-07-29T13:01:08Z")
Hi Jnettlet, Thanks very much. Issue fixed with your patch. Thanks!