# Enabling single-DIMM operations in the secondary DIMM slot

**URL:** <https://community.solid-run.com/t/enabling-single-dimm-operations-in-the-secondary-dimm-slot/1068>\
**Category:** NXP LX2160\
**Tags:** NXP-LX2160\
**Created:** [September 11, 2025, 6:16pm UTC](https://community.solid-run.com/t/enabling-single-dimm-operations-in-the-secondary-dimm-slot/1068 "2025-09-11T18:16:18Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![romameie](https://avatars.discourse-cdn.com/v4/letter/r/0ea827/32.png) [@romameie](https://community.solid-run.com/u/romameie)\
**Post date:** [September 11, 2025, 6:16pm UTC](https://community.solid-run.com/t/enabling-single-dimm-operations-in-the-secondary-dimm-slot/1068/1 "2025-09-11T18:16:18Z")

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I am in possession of a LX2160A CEx7 CoM with a broken primary DIMM slot.

Firmware images fail to boot with a DIMM in the secondary DIMM slot, because there is a bug after disabling the first DDR controller in the upstream ATF-A NXP DDR code.

I have opened an issue with ATF-A here [nxp ddr: Unused first DDRC is disabled improperly · Issue #144 · TrustedFirmware-A/trusted-firmware-a · GitHub](https://github.com/TrustedFirmware-A/trusted-firmware-a/issues/144) , outlining the problem and the solution (a single-line change).

The slightly clumsy way of applying the change is to clone

> **[GitHub - SolidRun/lx2160a\_build: Scripts to build basic images for LX2160A COM...](https://github.com/SolidRun/lx2160a_build)**
>
> Scripts to build basic images for LX2160A COM express type 7 modules

Then running an arbitrary build once.

Then change in build/atf/drivers/nxp/ddr/nxp-ddr/utility.c line 147 from

```auto
priv->phy[0] = priv->phy[0];

```

to

```auto
priv->phy[0] = priv->phy[1];

```

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<div class="post-metadata">

**Author:** ![romameie](https://avatars.discourse-cdn.com/v4/letter/r/0ea827/32.png) [@romameie](https://community.solid-run.com/u/romameie)\
**Post date:** [February 25, 2026, 6:40pm UTC](https://community.solid-run.com/t/enabling-single-dimm-operations-in-the-secondary-dimm-slot/1068/2 "2026-02-25T18:40:23Z")

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Update: A fix for this issue was merged into upstream ARM TF-A.

> <https://github.com/TrustedFirmware-A/trusted-firmware-a/commit/3c7ec07a00424779a55064fe27d50ed270f6442b>
>
> Fixes an issue where the first DDRC is disabled improperly
> when two DDRCs are pr…esent and only the second DDRC slot is
> populated with a DIMM.
> 
> Change-Id: Ia4f71c5e79fa318a81a291080494f25e76fd987f
> Signed-off-by: Roman Meier \<romameie@outlook.com\>

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<div class="post-metadata">

**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [March 11, 2026, 9:17am UTC](https://community.solid-run.com/t/enabling-single-dimm-operations-in-the-secondary-dimm-slot/1068/3 "2026-03-11T09:17:14Z")

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Thanks for your input. Yes this fix has been integrated in all the latest BSPs.