# Clearfog pro mpcie0 with 4 lane

**URL:** <https://community.solid-run.com/t/clearfog-pro-mpcie0-with-4-lane/604>\
**Category:** OCTEON CN9130\
**Created:** [March 23, 2023, 10:02am UTC](https://community.solid-run.com/t/clearfog-pro-mpcie0-with-4-lane/604 "2023-03-23T10:02:05Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![doudootiana](https://avatars.discourse-cdn.com/v4/letter/d/5f8ce5/32.png) [@doudootiana](https://community.solid-run.com/u/doudootiana)\
**Post date:** [March 23, 2023, 10:02am UTC](https://community.solid-run.com/t/clearfog-pro-mpcie0-with-4-lane/604/1 "2023-03-23T10:02:05Z")

</div>

Hy,  
I seen this topic for the model base : [https://community.solid-run.com/t/clearfog-base-cn9130-pcie0-4-lane-configuration/279](https://community.solid-run.com/t/clearfog-base-cn9130-pcie0-4-lane-configuration/279)

But i didn’t find the anwser 🙂

I would like to increase the number of lanes for mpcie0 to use wifi 6e card.

```auto
/* SRDS #4 - mini PCIe slot near SOM */
&cp0_pcie1 {
	status = "okay";
	phys = <&cp0_comphy4 1>;
	num-lanes = <4>;
	reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
};

/* SRDS #5 - mini PCIe slot far from SOM */
&cp0_pcie2 {
	status = "okay";
	phys = <&cp0_comphy5 2>;
	num-lanes = <1>;
	reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
};

```

I tried to modify the dts but it doesn’t work :

```auto
# sudo lspci -vv | grep -P "[0-9a-f]{2}:[0-9a-f]{2}\.[0-9a-f]|LnkSta:"
0000:00:00.0 PCI bridge: Marvell Technology Group Ltd. 88F8040 PCI Express controller (prog-if 00 [Normal decode])
                LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok)
0000:01:00.0 Network controller: Qualcomm Atheros QCA986x/988x 802.11ac Wireless Network Adapter
                LnkSta: Speed 2.5GT/s (ok), Width x1 (ok)
0001:00:00.0 PCI bridge: Marvell Technology Group Ltd. 88F8040 PCI Express controller (prog-if 00 [Normal decode])
                LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok)
#

```

Thanks by advance

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<div class="post-metadata">

**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [March 23, 2023, 10:25am UTC](https://community.solid-run.com/t/clearfog-pro-mpcie0-with-4-lane/604/2 "2023-03-23T10:25:55Z")

</div>

As a standard mini-PCIe only supports a single PCIe lane. Only m.2 connectors support up to 4 lanes.

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<div class="post-metadata">

**Author:** ![doudootiana](https://avatars.discourse-cdn.com/v4/letter/d/5f8ce5/32.png) [@doudootiana](https://community.solid-run.com/u/doudootiana)\
**Post date:** [March 23, 2023, 10:30am UTC](https://community.solid-run.com/t/clearfog-pro-mpcie0-with-4-lane/604/3 "2023-03-23T10:30:18Z")

</div>

Hy  
Thank you for your answer 🙂

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<div class="post-metadata">

**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [March 23, 2023, 10:33am UTC](https://community.solid-run.com/t/clearfog-pro-mpcie0-with-4-lane/604/4 "2023-03-23T10:33:55Z")

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A single PCIe gen 3 lane effectively supports up to 984 MB/s per lane. Even with protocol overhead that is still more than enough bandwidth to support even the fastest wireless protocols.

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<div class="post-metadata">

**Author:** ![doudootiana](https://avatars.discourse-cdn.com/v4/letter/d/5f8ce5/32.png) [@doudootiana](https://community.solid-run.com/u/doudootiana)\
**Post date:** [March 24, 2023, 10:48pm UTC](https://community.solid-run.com/t/clearfog-pro-mpcie0-with-4-lane/604/5 "2023-03-24T22:48:26Z")

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![image_2023-03-24_234750251](https://europe1.discourse-cdn.com/flex005/uploads/solid_run/original/1X/1ec896e26c63c773e2b250f97e0041938cdbefac.jpeg)

hy

I tested with a rj45 2.5gbps, connected in the pcie.

Good surprise 🙂