# Change DPMAC17@rgmii-id PHY\_ADDR from 0x1 to 0x5 failed in u-boot

**URL:** <https://community.solid-run.com/t/change-dpmac17-rgmii-id-phy-addr-from-0x1-to-0x5-failed-in-u-boot/696>\
**Category:** Uncategorized\
**Created:** [August 2, 2023, 7:27am UTC](https://community.solid-run.com/t/change-dpmac17-rgmii-id-phy-addr-from-0x1-to-0x5-failed-in-u-boot/696 "2023-08-02T07:27:39Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![ChuandeChen](https://avatars.discourse-cdn.com/v4/letter/c/ecae2f/32.png) [@ChuandeChen](https://community.solid-run.com/u/ChuandeChen)\
**Post date:** [August 2, 2023, 7:27am UTC](https://community.solid-run.com/t/change-dpmac17-rgmii-id-phy-addr-from-0x1-to-0x5-failed-in-u-boot/696/1 "2023-08-02T07:27:39Z")

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Hi All,

I tried to change DPMAC17@rgmii-id PHY\_ADDR from 0x1 to 0x5 in u-boot, but failed.  
Is there any other code I need to change?

I changed below file, but looks the phy addr is still 1 in u-boot.

— a/include/configs/lx2160acex7.h  
+++ b/include/configs/lx2160acex7.h  
@@ -42,7 +42,7 @@  
#define CONFIG\_MII  
#define CONFIG\_ETHPRIME “DPMAC17@rgmii-id”

-#define RGMII\_PHY\_ADDR1 0x01  
+#define RGMII\_PHY\_ADDR1 0x05

uboot log:

NOTICE: BL2: v2.4(release):LSDK-21.08-8-g68852f7e8  
NOTICE: BL2: Built : 07:34:31, Aug 1 2023  
NOTICE: UDIMM KF3200C20S4/16G  
NOTICE: DDR PMU Hardware version-0x1210  
NOTICE: DDR PMU Firmware vision-0x1001 (vA-2019.04)  
NOTICE: DDR4 UDIMM with 1-rank 64-bit bus (x8)

NOTICE: 32 GB DDR4, 64-bit, CL=20, ECC off, 256B  
NOTICE: BL2: Booting BL31  
NOTICE: BL31: v2.4(release):LSDK-21.08-8-g68852f7e8  
NOTICE: BL31: Built : 07:34:31, Aug 1 2023  
NOTICE: Welcome to lx2160acex7 BL31 Phase

U-Boot 2021.04-00040-gebf041ec9b-dirty (Aug 01 2023 - 07:34:26 +0000)

SoC: LX2160ACE Rev2.0 (0x87360020)  
Clock Configuration:  
CPU0(A72):2000 MHz CPU1(A72):2000 MHz CPU2(A72):2000 MHz  
CPU3(A72):2000 MHz CPU4(A72):2000 MHz CPU5(A72):2000 MHz  
CPU6(A72):2000 MHz CPU7(A72):2000 MHz CPU8(A72):2000 MHz  
CPU9(A72):2000 MHz CPU10(A72):2000 MHz CPU11(A72):2000 MHz  
CPU12(A72):2000 MHz CPU13(A72):2000 MHz CPU14(A72):2000 MHz  
CPU15(A72):2000 MHz  
Bus: 700 MHz DDR: 3200 MT/s  
Reset Configuration Word (RCW):  
00000000: 50838338 24500050 00000000 00000000  
00000010: 00000000 0e010000 00000000 00000000  
00000020: 10c001a0 00002580 00000000 08000086  
00000030: 09240000 00000001 00000000 00000000  
00000040: 00000000 00000000 00000000 00000000  
00000050: 00000000 00000000 00000000 00000000  
00000060: 00000000 00000000 00027000 00000000  
00000070: 08a80001 00151020  
Model: SolidRun LX2160ACEX7 COM express type 7 based board  
Board: LX2160ACE Rev2.0-CEX7, eMMC

Net: Could not get PHY for mdio@8b96000: addr 1  
eth0: DPMAC3@xgmii, eth1: DPMAC4@xgmii, eth2: DPMAC5@xgmii, eth3: DPMAC6@xgmii, eth4: DPMAC7@xgmii, eth5: DPMAC8@xgmii, eth6: DPMAC9@xgmii, eth7: DPMAC10@xgmii, eth8: DPMAC17@rgmii-id [PRIME]  
switch to partitions #0, OK

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<div class="post-metadata">

**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\
**Post date:** [August 2, 2023, 7:32am UTC](https://community.solid-run.com/t/change-dpmac17-rgmii-id-phy-addr-from-0x1-to-0x5-failed-in-u-boot/696/2 "2023-08-02T07:32:47Z")

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Is this for a custom board design? Generally now the phy’s are read from device-tree, you will find them in `arch/arm/dts/fsl-lx2160a-cex7.dts`

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<div class="post-metadata">

**Author:** ![ChuandeChen](https://avatars.discourse-cdn.com/v4/letter/c/ecae2f/32.png) [@ChuandeChen](https://community.solid-run.com/u/ChuandeChen)\
**Post date:** [August 2, 2023, 12:13pm UTC](https://community.solid-run.com/t/change-dpmac17-rgmii-id-phy-addr-from-0x1-to-0x5-failed-in-u-boot/696/3 "2023-08-02T12:13:37Z")

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Thanks jnettlet! It works!