# CEX7: SD1 Modification **URL:** \ **Category:** NXP LX2160\ **Created:** [October 23, 2023, 4:47pm UTC](https://community.solid-run.com/t/cex7-sd1-modification/750 "2023-10-23T16:47:13Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![neiljones](https://avatars.discourse-cdn.com/v4/letter/n/58f4c7/32.png) [@neiljones](https://community.solid-run.com/u/neiljones)\ **Post date:** [October 23, 2023, 4:47pm UTC](https://community.solid-run.com/t/cex7-sd1-modification/750/1 "2023-10-23T16:47:13Z")
After applying the following modification to our ComE module the board fails to boot: [https://solidrun.atlassian.net/wiki/spaces/developer/pages/197493994/LX2160A+COM+Hardware+User+Manual#SERDES-block-%231-(SD1)](https://solidrun.atlassian.net/wiki/spaces/developer/pages/197493994/LX2160A+COM+Hardware+User+Manual#SERDES-block-%231-(SD1)) We get nothing on the terminal, it seems like its in some fast reset loop as I can hear the fan pulsating. I’ve tried SD and eMMC boot, the SPI flash was not programmed prior to the mod when the board was working fine. I’m fairly confident the mod is applied correctly and we can measure a 100MHz clock on both sides of both 0R links and a 160Mhz clock on both sides of both capacitors. I assume there is a typo in the instructions which says to move one of the 0R links to R **2** 381 we assumed R381 was intended. I guess its possible something got damaged during the mod, but it was done in an ESD safe lab and we have inspected the board thoroughly under our microscope and all looks well. Is there anyway of getting more diagnostics on a failed boot beyond UART, I guess JTAG is the only option ? Is this enabled early on in boot, is the jtag interface secured somehow ? I could try reverting the mod, but its tricky as they are very small parts placed close to the main SoC, so want to exhaust other options first. And can you ask your hardware guys to at least use 0603 parts for interchangable/configurable components like this in the future! ---
**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\ **Post date:** [October 23, 2023, 5:05pm UTC](https://community.solid-run.com/t/cex7-sd1-modification/750/2 "2023-10-23T17:05:27Z")
Have you also changed the RCW configuration to reflect the clock changes you made for SERDES 1? ---
**Author:** ![neiljones](https://avatars.discourse-cdn.com/v4/letter/n/58f4c7/32.png) [@neiljones](https://community.solid-run.com/u/neiljones)\ **Post date:** [October 23, 2023, 5:29pm UTC](https://community.solid-run.com/t/cex7-sd1-modification/750/3 "2023-10-23T17:29:10Z")
Yes, SD1 was coming up as PCIe before the mod, just gen2 not gen3, I’m using 1\_13\_3 config (all PCIe). Would the board fail to boot if these clocks are not present though, PCIe/Serdes is not required for initial boot, isn’t TF-A running from ROM then loading BL2/3 from SD / eMMC / SPI ?? Surely I should get something on UART ? ---
**Author:** ![jnettlet](https://dub1.discourse-cdn.com/flex005/user_avatar/community.solid-run.com/jnettlet/32/62_2.png) [@jnettlet](https://community.solid-run.com/u/jnettlet)\ **Post date:** [October 23, 2023, 5:34pm UTC](https://community.solid-run.com/t/cex7-sd1-modification/750/4 "2023-10-23T17:34:42Z")
The service processor configures the clocks and SERDES among other things via the RCW and PBL, before any other boot stages are attempted. If this fails then boot will hang or reset before there is any output on the serial console. The RCW setup for PLLF and PLLS need to reflect how the hardware is configured. ---
**Author:** ![neiljones](https://avatars.discourse-cdn.com/v4/letter/n/58f4c7/32.png) [@neiljones](https://community.solid-run.com/u/neiljones)\ **Post date:** [October 24, 2023, 10:45am UTC](https://community.solid-run.com/t/cex7-sd1-modification/750/5 "2023-10-24T10:45:52Z")
Cheers, So I’m using the 1\_13\_3 Serdes configuration, but it appears after making this mod you need to use the 1 **S** \_13\_3 configuration, I’m not in the office today so cannot test it, but fingers crossed this will work. ---
**Author:** ![neiljones](https://avatars.discourse-cdn.com/v4/letter/n/58f4c7/32.png) [@neiljones](https://community.solid-run.com/u/neiljones)\ **Post date:** [October 26, 2023, 1:18pm UTC](https://community.solid-run.com/t/cex7-sd1-modification/750/6 "2023-10-26T13:18:49Z")
I can confirm that using the **1S** \_13\_3 configuration fixed my none booting issue, cheers! Maybe you should add that info to the hardware wiki, along with the mod details.